Informatics Publishing Limited

Mohammed Altaf Ahmed ¹, D. Elizabeth Rani ¹, Syed Abdul Sattar ²

Affiliations
1 GITAM Institute of Technology, GITAM University, Visakhapatnam – 531173, Andhra Pradesh, IN
2 Royal Institute of Technology and Science, Chevella – 501503, Andhra Pradesh, IN

Abstract

In the current high speed, low power VLSI Technology design, Built in Self Test (BIST) is emerging as the most essential part of System on Chip (SoC). The industries are flooded with diverse algorithms to test memories for faults. The March based algorithms are become popular so quickly for locating faults in memories. This research study attempt to design the memory BIST controller for March 17N as selected algorithm. It tests various memories for faults. A simple architecture is implemented in Verilog Hardware Description Language (HDL), which can be easily integrate with SoC and is able to locate the fault location in the semiconductor memories. Integration of memory BIST controller in SoC design improves chip yield. The design has achieved 497.47MHzof maximum frequency by use of only 158 slice LUTs on Virtex-7 Field Programming Gate Array (FPGA) device. The proposed memory BIST controller is suitable for SoC integration to test various memories at high speed with very low area overhead.

Keywords

Low Area, Memory BIST, SoC Integration, Test Memories, Yield Improvement

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Shaik Qadeer ¹, Mohammed Zafar Ali Khan ², Syed Abdul Sattar ³

Affiliations
1 Department of Electrical & Electronics Engineering, Muffakham Jah College of Engineering and Technology, IN
2 Department of Electrical Engineering, Indian Institute of Technology Hyderabad, IN
3 Department of Electrical and Electronics Engineering, Royal Institute of Technology and Science, IN

Abstract

In this paper we present alternate form of Radix-4/8 and split radix FFT’s based on DIF (decimation in frequency) version and discuss their implementation issues that further reduces the arithmetic complexity of power-of-two discrete Fourier Transform. This is achieved with circular shift operation on a subset of the output samples resulting from the decomposition in these FFT algorithms and a proposed dynamic scaling. These modifications not only provide saving in the calculation of twiddle factor, but also reduce the total flop count to ≈4Nlog₂N almost 6% fewer than the standard Radix-4 FFT algorithm ≈ 3×11/12Nlog₂N, 5% fewer than the standard Radix-8 FFT, and ≈3×7/9Nlog₂N, 5.5% fewer than the standard split radix FFT.

Keywords

DFT (Discrete Fourier Transform), FFT (Fast Fourier Transform), Radix-4(R4), Radix-8(R8) and Split Radix (SR) FFT and Flop Count.

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Nisar Ahmed ¹, Syed Abdul Sattar ²

Affiliations
1 Department of Electronics and Communication Engineering, Mewar University, IN
2 Department of Electronics and Communication Engineering, Nawab Shah Alam Khan College of Engineering and Technology, IN

Abstract

The main intention of Fractal Image Compression is to reduce the size of image and maintain good level of their reconstructed image. A major issue in Fractal Image Compression is decrease in image quality, compression ratio and PSNR. To overcome these issues we employ Fractal transformation with entropy coding. There are two phases in the proposed approach. In the first phase color images are separated into three RGB planes using variable range block size. In second phase by applying the inverse transform and iterative functions the image is restored. It is observed that the results are improving in fractal compression for both gray images as well as color images. In this work high CR and PSNR is observed compared to fixed block range and other existing methods. The proposed work yields better CR of 20 and high PSNR.

Keywords

Fractal Image Compression, Variable Block Size, CR, PSNR.

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